1. Field of the Invention
The present invention is directed to precise waveform peak detection, and is more particularly directed to an apparatus and methodology which efficiently provides high accuracy peak amplitude and time identification for a wide bandwidth.
2. Description of Related Art
Analog peak detectors generally fall into two categories; very accurate with a narrow bandwidth or inaccurate with a wide bandwidth. At low frequencies (e.g., audio), it is possible to use operational amplifiers to build precision peak detectors. These configurations can be very accurate, but fall prey to narrow bandwidth limitations. Other analog designs have much wider bandwidths (up to a few MHz), but fall prey to inaccuracies that are due to non-linear gain functions which limit useful operation to a small amplitude range. Furthermore, their use is generally acceptable only when errors of several percent can be tolerated.
The alternate approach to analog peak detection is through digital analysis of waveforms. This involves the use of an analog-to-digital converter (ADC) that digitizes an input signal with an evaluation of the resulting discrete values conducted in order to identify signal peaks and their corresponding characteristics (i.e., amplitude and time of occurrence). One particular method consists of very high speed ADC sampling and subsequent digital magnitude comparisons. While this is a straightforward approach, typically the sample rate of an ADC is not fast enough to guarantee that a data point is taken at the exact time of the signal peak. Instead, a sample on either side of the peak is identified as the true peak, thereby resulting in a reported peak value which is somewhat smaller than the actual value.
For high frequency input signals, e.g. several MHZ, it is also difficult to obtain an ADC sample rate that is sufficient to provide high precision identification. For a simple sine wave input, the minimum required sample rate that provides an accuracy of 0.01% is 223 times the input frequency. Currently, the fastest single twelve bit ADC chip has a maximum sample rate of approximately 40 million samples per second (MSPS), which would limit the input frequency to 400 kHz if the sample error is to be less than 0.05%, or 4.0 MHZ for an error no larger than 1.0%.
It is possible to increase the effective sampling rate of an ADC by incorporating an interpolation circuit. With an interpolation circuit, additional samples are provided between the measured points. However, the drawback is that the input bandwidth must be limited to avoid inducing errors into the interpolated values.
Faster sampling rates may also be obtained by using ten bit, eight bit, or six bit ADCs. However, the accuracy is then limited by the resolution of the ADC. Generally, the nominal input signal is scaled to approximately two-thirds of full scale. At this input sampling rate, the error due to ADC quantization is 0.073% for a twelve bit ADC, 0.293% for a ten bit ADC, 1. 172% for an eight bit ADC, and 4.688% for a six bit ADC. Therefore, current ADC technology provides peak detection that is limited to low frequencies (less than about 1 MHZ) if good accuracy (better than about 0.5%) is required. Furthermore, at high sample rates, it is difficult to design a digital magnitude comparator which will adequately examine the ADC output for peak identification. In addition, this method provides a peak time which is only known to within one ADC sample interval, which is not accurate enough for some applications.
An additional ADC peak determination methodology consists of utilizing an ADC that is triggered to measure only at the input signal peaks. This method has the problem of generating an appropriate trigger signal. It is not possible to generate a trigger at the time of the peak, but rather a trigger is presented which is delayed by a fixed amount of time after the peak has occurred. This is due to the process selecting a peak based upon a detected decrease in amplitude. Therefore, the analog signal must be delayed without distortion and the delay must exactly equal the delay in the trigger circuit. However, it is very difficult to build a wide band analog delay which does not distort the input signal. In addition, it is also very difficult to match the delays of the trigger circuit and the analog delay.
The trigger circuit must detect the time of the peak with great accuracy. The delay from the input signal peak to the trigger output must also be very stable. Timing variation in the trigger circuit causes significant error in the recorded peak value. If a desired amplitude accuracy of 0.05% is desired, the differences in the time delay of the analog delay element and the trigger channel must be 5.03.times.10.sup.-3 the input period. For example, with a one MHZ sine wave input, a timing accuracy of .+-.7.1 nanoseconds is required to maintain an amplitude accuracy of 0.1%. Furthermore, to determine the timing of the peaks requires additional circuitry (i.e., a digital time interval analyzer which measures the timing of a trigger output).
Based upon the foregoing, it is an object of the present invention to provide peak detection which has a high degree of accuracy for a wide bandwidth. Furthermore, it is an object of the present invention to provide the accurate and wide bandwidth peak detection using an apparatus and methodology which is relatively inexpensive to implement.